The present invention relates to an all-silicon oscillator for an integrated circuit whose use is to generate phase clock signals for controlling the operation of various circuits in a VLSI system.
Modern digital integrated circuits typically include a master clock from which there are generated 4 phase clock signals. The master clock employs a Schmitt trigger circuit whose input is coupled to a capacitor that is connected to ground and which is charged through a resistor from a high voltage source. A field effect transistor has its source-to-drain path coupled around the capacitor and its gate connected to the output of the Schmitt trigger in order to discharge the capacitor in response to the latter output going high. Upon the voltage rise across the capacitor increasing to a level V.sub.H the Schmitt trigger switches and turns on the field effect transistor thereby discharging the capacitor. As the input voltage to the Schmitt trigger falls and reaches a value V.sub.L it then switches so that its output falls turning off the transistor connected across the capacitor and turning on the one in series with the resistor thereby repeating the cycle. Various clock signals are derived from the output of the Schmitt trigger by using divide by two circuits in combination with logic circuits. Thus, the repetition rate of the master clock must be at least 4 times faster than the repetition rate of the 4 clocks in the latter system. The slower frequency of the 4 clocks also reduces the power obtainable when such circuits are used as voltage multipliers or charge pumps. Secondly, the duty cycle of the Schmitt trigger output is normally significantly less than 50% for such a system since the discharge time of the capacitor is generally significantly less than its charge time.
Accordingly, it is a principal object of the invention to provide an oscillator that produces clock pulses whose frequency is equal to or greater than that of the oscillator. It is a further object of the invention to provide an oscillator having a duty cycle that is substantially equal to 50%.